The present invention relates to a method for fabricating a semiconductor memory device; and, more particularly, to a method for fabricating a CMOS transistor.
A complementary metal oxide semiconductor (CMOS) transistor includes a nMOS transistor and a pMOS transistor. If the CMOS transistor is used for configuring a peripheral circuit of a memory device of 0.18 xcexcm and below, the COMS transistor includes the 0.25 xcexcm and larger nMOS and pMOS transistors having a gate length larger than a minimum line width. The above mentioned CMOS transistor is configured by concurrently forming a lightly doped drain (LDD) region of a surface channel nMOS transistor and a punch stop layer of a buried channel pMOS transistor. The LDD region and the punch stop layer is formed by ion implantation of an n-type dopant such as phosphorus (P) into a forming region of the nMOS transistor and a forming region of the pMOS transistor without using a mask.
FIGS. 1A to 1B are cross-sectional views showing a conventional process for fabricating a CMOS transistor.
Referring to FIG. 1A, after forming a device isolation layer for isolating each of devices in a semiconductor substrate 11, a n-type well 13 is formed on a region of a pMOS transistor in the semiconductor substrate 11 and continuously an n-type field stop layer 14 is formed in the n-type well 13. A p-type well 15 is formed on a nMOS transistor region in the semiconductor substrate 11 and a p-type field stop layer 16 is formed on the p-type well 15.
After forming the p-type field stop layer 16, a gate oxide layer 17 and a gate electrode 18 is formed on a selected region on the semiconductor substrate 11 providing the pMOS transistor and nMOS transistor. Finally, there formed an n-type punch stop layer 20 on the pMOS transistor and an n-type LDD 21 on the nMOS transistor by ion-implanting phosphorus (P) by using a blanket ion implantation and depositing a nitride layer 19 on the above entire structure.
Referring to FIG. 1B, after an oxide layer (not shown) is deposited on the entire structure, a spacer 22 contacting to lateral sides of the gate electrode 18 is formed by an etch-back process. At this time, the nitride layer 19 and the gate oxide layer 17 are concurrently proceeded with an etch-back process applied to an upper surface of the semiconductor substrate 11. Reference numerals 19A and 17A are a remaining nitride layer and a remaining gate oxide layer, respectively.
Next, a p-type source/drain region 23 is formed by ion-implanting a p-type impurity in the pMOS transistor region, and an n-type source/drain region 24 is also formed by ion-implanting an n-type impurity on the nMOS transistor region.
In FIGS. 1A and 1B, when the n-type LDD doping layer 21 is formed on the nMOS transistor region, the n-type punch stop layer 20 is also formed on the pMOS transistor region.
However, in the above mentioned conventional method for fabricating the CMOS transistor, optimum characteristics of the nMOS transistor and the pMOS transistor cannot be obtained, since forming conditions for the LDD region of the nMOS transistor and the punch stop layer of the pMOS transistor are identical. As a result, one of the characteristics of the nMOS transistor and the pMOS transistor is degraded.
Furthermore, the above mentioned conventional method cannot control a short channel effect provided by each of the nMOS transistor and the pMOS transistor since a gate length of a peripheral circuit is below 0.25 xcexcm in the memory device of above 0.15 xcexcm.
For example, when the n-type impurity is ion-implanted for concurrently forming the LDD region and the punch stop layer, the short channel effect of the pMOS transistor is constrained according to an amount of the n-type impurity for ion-implantation, however, the short channel characteristic of the nMOS transistor is degraded. Also, when the n-type impurity is ion-implanted with a minimally increased quantity for increasing driving current of the nMOS transistor, a threshold voltage VT is dynamically increased and the driving current is decreased. Therefore, reducing the gate length of the MOS transistor provides a limitation in a fabricating process for the CMOS transistor.
For overcoming the above mentioned problem, another conventional CMOS transistor fabricating method is introduced by Takashi Hori et al., at xe2x80x9cA 0.1 xcexcm CMOS technology with tilt-implanted punch through stopper (TIPS)xe2x80x9d IEDM, 1994 (hereinafter Takashi). The Takashi teaches a method for fabricating a CMOS transistor having a gate length around 0.1 xcexcm. The Takashi""s method individually performs ion-implantations to form the punch stop structure of a surface channel nMOS transistor and a buried channel pMOS transistor by using different masks.
FIG. 2 is a cross-sectional view of a CMOS transistor for explaining the Takashi""s forming process of a CMOS transistor.
Referring to FIG. 2, a gate oxide layer 25 and a gate electrode 26 are formed on a semiconductor substrate 24, and a spacer 27 is formed on both lateral sides of the gate electrode 26. A LDD region 28 is formed at edges on both sides of the gate electrode 26 in the nMOS transistor region. An n+ source/drain region is formed by contacting to the LDD region 28, and the p-type punch stop layer 30 is formed on a bottom of the LDD region 28 by performing the tilted ion implantation of boron (B). In the pMOS transistor region, a p+ source/drain region 31 is formed and an n-type punch stop layer 32 is formed on a side of the p+ source/drain region 31 by tilted ion implanting phosphorus (P).
Atsuki Hori et al. introduces another method for fabricating a CMOS transistor in xe2x80x9cA 0.05 xcexcm CMOS with ultra shallow source/drain junctions fabricated by 5 KeV ion imimplantation and rapid thermal annealingxe2x80x9d IEDM, 1994 (Hereinafter Atsuki). The Atsuki""s method teaches to fabricate the nMOS transistor and the pMOS transistor in order to have a gate of 0.5 nm by using a self aligned pocket implantation (SPI) and a source/drain extension (SDE).
FIG. 3 is a cross-sectional view of a CMOS transistor for explaining the Atsuki""s forming process.
Referring to FIG. 3, a gate oxide layer 34 and a gate electrode 35 are formed on a semiconductor substrate 33. Also, a spacer 36 is formed on both lateral sides of the gate electrode 35. An n+ source/drain extension region 37A is formed on both edges of the gate electrode 35 in the nMOS transistor region. An n+ source/drain region 38B is formed by contacting to the n+ source/drain extension region 37A. A p-type self aligned pocket layer is formed beneath of the n+ source/drain extension region 37A by tilted ion-implanting boron (B). An n-type self aligned pocket layer 39A and a p+ source/drain extension region 37A are formed on both edges of the gate electrode 35 in the pMOS transistor region. A p+ source/drain region 38B is formed by contacting to the p+ source/drain extension region 37B and the n-type self aligned pocket layer 39B.
As mentioned above, the Atsuki and Takasi provide methods that optimize characteristics of the nMOS transistor and the pMOS transistor. However, the methods use different masks for each of nMOS transistor region and pMOS transistor region. Additional processes such as a LDD doping process and a source/drain extension region process are performed. As a result, a complexity of a fabricating process is increased and a manufacture expense is also increased. Therefore, the above mentioned methods are incongruent for manufacturing a semiconductor memory device.
Specially, in case of the Atuski"" method, arsenic (AS) is used for forming the source/drain extension region of the nMOS transistor. As a result, a problem with respect to a hot carrier is arose when the nMOS transistor is used in one of peripheral circuits, which require a higher driving voltage such as an external voltage.
Therefore, it has been demanded that a simple and low cost method for fabricating a CMOS transistor in order to be implemented to a semiconductor device of 0.15 xcexcm, wherein the method can maintain optimum characteristics of the nMOS transistor and pMOS transistor and prevent the hot carrier problem.
It is, therefore, an object of the present invention to provide a simple and low cost method for fabricating a CMOS transistor in order to constrain a short channel effect and a hot carrier effect.
In accordance with an aspect of the present invention, there is provided a semiconductor, comprising a gate electrode and a gate oxide layer on a semiconductor substrate; spacers formed on sides of the layer; a first conductive type source/drain region formed at edge of the spacers in the semiconductor substrate; a second conductive type punch stop layer formed in a region between the first conductive type source/drain region in the semiconductor substrate; a first conductive type source/drain extension region occupying a extended region from the first conductive type source/drain region to the both edges of the gate electrode; and a first conductive type lightly doped drain (LDD) region being adjoined to the source/drain region and surrounding the source/drain extension region, wherein the junction depth of the first conductive type LDD region is constrained by the punch stop layer.
In accordance with another aspect of the present invention, there is also provided a semiconductor device, comprising: a semiconductor substrate having a nMOS region and a pMOS region; a gate electrode and a gate oxide layer formed on each of the nMOS region and the pMOS region; spacers contacted to sides of the layer; a p-type source/drain region formed in the pMOS region by lining up at edges of the spacers; a n-type source/drain region formed in the nMOS region by lining up at edges of the spacers; a first punch stop layer formed by overlapped on bottom of the p-type source/drain region; a second punch stop layer formed by contacting to one side of the p-type source/drain region and on the bottom of the spacers; a third punch stop layer formed by contacting to one side of the n-type source/drain region; a source/drain extension region formed by contacting to one side of the n-type source/drain region and on bottom of the spacers; and a lightly doped drain (LDD) region surrounding the source/drain extension region.
In accordance with still another aspect of the present invention, there is also provided A method for fabricating a CMOS transistor, comprising: a) forming a n-type well region in a semiconductor substrate; b) forming a first n-type punch stop layer in the n-type well; c) forming a p-type well region in the n-type well region; d) concurrently forming a first n-type LDD region in the p-type well region and a second n-type punch stop layer in the n-type well region by ion-implanting an impurity to the gate electrode as a mask; e) forming a n-type source/drain extension region having higher concentration of the impurity than the first LDD region in the first LDD regions; f) forming a second n-type LDD region, which surrounds the n-type source/drain extension region; g) forming a spacer at a side of the gate electrode; h) forming p-type source/drain region contacting to the first punch stop layer and the second punch stop layer; and i) forming a n-type source/drain region contacting to the source/drain extension region and the first and second LLD region.